Variability Measures of Positive Random Variables

During the stationary part of neuronal spiking response, the stimulus can be encoded in the firing rate, but also in the statistical structure of the interspike intervals. We propose and discuss two information-based measures of statistical dispersion of the interspike interval distribution, the entropy-based dispersion and Fisher information-based dispersion. The measures are compared with the frequently used concept of standard deviation. It is shown, that standard deviation is not well suited to quantify some aspects of dispersion that are often expected intuitively, such as the degree of randomness. The proposed dispersion measures are not entirely independent, although each describes the interspike intervals from a different point of view. The new methods are applied to common models of neuronal firing and to both simulated and experimental data

DSPs, GPPs, and Multimedia Applications - An Evaluation Using DSPstone

The DSPstone evaluation methodology is applied to evaluate performance of fixed-- and floating--point digital signal (DSP), and general purpose (GPP) processors with appropriate C compilers. Main goal was to estimate run-- time efficiency on code which is representative for baseband processing in multimedia applications. The results show that for DSP--type code, like FIR filtering, DSP processors are superior compared to GPP processors, both in processor and C compiler performance. Also, it is shown that contrary to an established opinion, C compilers for floating--point DSP and GPP processors introduce significant run-time overhead on DSP-type code. This overhead mostly disappears if the programming of fixed-- and floating--point DSP processors is done using language extensions. I. Introduction The digital signal processing (DSP) market is no longer a small niche of the overall computer market. Especially in multimedia and mobile communications, the market for fixed-point and floati..

Supersim - A New Technique For Simulation Of Programmable DSP Architectures

This paper presents a technique for simulating DSP processors based on the principle of compiled simulation. Unlike existing, commercially available instruction set simulators for DSP processors, which are of interpretive character, the proposed technique performs instruction decoding and simulation scheduling at compile time. The technique offers up to three orders of magnitude faster simulation. The high speed allows the user to explore algorithms and hardware /software trade-offs before any hardware implementation. Moreover, the user can tailor the compiled simulation to trade speed for more accuracy. In this paper, the sources of the immense speedup are analyzed and the realization of the simulation compiler is presented. I. Introduction Designers of today's DSP systems --- such as digital cellular phones and multimedia systems --- face rising complexity and quickly changing system requirements. To deal with these challenges, designers have increasingly turned to programmable arc..

Binary acceleration using coarse-grained reconfigurable architecture

Coarse-grained reconfigurable architectures (CGRAs) have been well-researched and shown to be particularly effective in acceleration of data-intensive applications. However, practical difficulties in application mapping have hindered their widespread adoption. Typically, an application must be modified manually or by using special compilers and design tools in order to fully exploit the architecture. This incurs considerable design costs to the application developer and reduces software portability. In this paper, we propose a framework for automatic transformation of an application at binary-level, with which the user can execute an arbitrary application on the CGRA. Our approach analyzes the binary code and determines which portions of the program to accelerate, maps them to the reconfigurable array, then modifies the binary code appropriately to run on the CGRA. We describe the overall process of our framework, and present solutions to several problems that arise from such an approach. Results from our preliminary experiments show that we are able to achieve speedup of up to 14.8.clos